1. Field of the Invention
The present invention relates to a code conversion method and apparatus for scrambling and modulating data, a code recording medium on which the scrambled and modulated data may be recorded and code recording and reproducing apparatus for recording/reproducing the scrambled and modulated data onto/from a recording medium.
2. Description of the Related Art
Optical disks have become very popular as recording media for recording various types of software data such as video data, audio data and computer data thereon. The optical disks include various kinds of read-only type disks such as a laser disk (LD), a compact disk (CD), a compact disk read-only memory (CD-ROM) and various kinds of rewritable and/or write-once type disks such as a magneto-optic disk, a phase change disk and a recordable compact disk (CD-R).
On the other hand, in recent years, high-efficiency coding technologies also have been developed. Consequently, any type of data currently can be processed as digital data. For example, even video data can be band compressed so as to be processed as digital data. In view of these developments, increasingly it has become necessary to further increase the capacity and the recording density of an optical disk.
However, as the recording density of a recording medium is increased, the difference between the signals representing a value of "1" and the signals representing a value of "0" which have been read out from such a recording medium becomes smaller. As a result, a read margin is adversely decreased and the quality of a reproduced signal is more likely to be degraded.
In order to avoid such a degradation in quality of a reproduced signal, the low frequency components of a signal must be reduced when the signal is recorded onto a recording medium. This is because a signal reproduced from an optical disk contains a lot of low frequency noise, which must be removed by a filter in order to improve the signal to noise (S/N) ratio of a reproduced signal. Thus, since the filter also cuts the necessary low frequency components of the reproduced signal, the effects of the noise reduction may be alleviated by preliminarily reducing the low frequency components of the signal to be recorded.
Various data coding methods have been proposed for reducing the low frequency components thereof. However, even when any of these coding methods is applied, a data pattern having low frequency components which cannot be reduced may still appear for a long duration in some cases. Thus, it is effective to scramble data for reducing the possibility.
When data is recorded and/or reproduced onto/from a recording medium, recording and reproducing operations are performed on the basis of a data unit having a particular size. Such a data unit is called a "sector". The run length of the codes recorded on a sector is limited in order to narrow the frequency bandwidth of a channel for the recording/reproducing apparatus.
Once an error is generated when the data is recorded and/or reproduced onto/from the run-length limited sector, the error does not remain in the erroneous sector but is propagated into succeeding sectors of the data. In order to prevent such error propagation, predetermined patterns identifiable from the recorded data are recorded onto every sector at regular intervals. Such patterns are called "sync codes". The respective regions of a sector which are partitioned by these sync codes are called "frames".
As mentioned above, since the low frequency components of data must be reduced when the data is recorded, the data is converted before the data is recorded. The conversion is accomplished, for example, by a code conversion apparatus such as that shown in FIG. 18.
As shown in FIG. 18, when main data is input to a scrambler 101, the scrambler 101 scrambles the main data in accordance with a pseudo-random number sequence and then supplies the scrambled main data to an 8/16 modulator 102. When the scrambled main data is input to the 8/16 modulator 102, the 8/16 modulator 102 modulates the main data and then outputs the modulated main data as recording data. The recording data is transmitted to a recording/reproducing apparatus to be recorded onto a recording medium.
In addition, the higher 4 bits (i.e., bit 4 to bit 8) of the logical address (8 bits) associated with the input main data is also input to the scrambler 101 as a seed select signal. Scramble data of different types are sequentially selected within a set of 16 logical addresses (i.e., on the basis of 16 sectors). That is to say, single scramble data is represented by any of respectively different 16 types of pseudo-random number sequences. Thus, in the respective sectors, the 16 types of pseudo-random number sequences associated with the respective scramble data are sequentially selected. Moreover, the scrambler 101 scrambles the data included in one sector depending upon the selected pseudo-random number sequences, in response to a sector start signal.
The scrambling is performed by the scrambler 101 by obtaining the exclusive-OR of the main data and the data (or random numbers) generated from an M sequence (maximum length sequence) represented by the following generating polynomial (1) for every bit of both types of data. EQU X.sup.15 +X.sup.4 +1 (1)
FIG. 19 illustrates a configuration of the scrambler 101. As shown in FIG. 19, the initial bit patterns of the 16 types of pseudo-random number sequences are stored beforehand in a seed ROM 111. In response to a seed select signal, any of these initial bit patterns is selected from the seed ROM 111. A shift register 112 receives the initial bit pattern selected from the seed ROM 111 in response to a seed load signal and then sequentially shifts the initial bit pattern in synchronization with a bit clock. An exclusive-OR element 113 obtains an exclusive-OR of the bit shifted out by the shift register 112 and the fourth most significant bit stored in the shift register 112 and then returns the operation result to the shift register 112. The lower 8 bits stored in the shift register 112 are latched in a flip-flop 114 in synchronization with a word clock. A corresponding bit of the 8-bit string latched in the flip-flop 114 is applied to an individual exclusive-OR element 115. Not only the corresponding bit of the 8-bit string but also a corresponding bit of 8-bit main data word are input to each of these exclusive-OR elements 115, which obtains the exclusive-OR of each pair of bits and then outputs the operation result.
On the other hand, the 8/16 modulator 102 performs a two-stage modulation to produce an output main data from the scrambled main data. The first stage modulation is performed to produce 16-bit main data from 8-bit main data by modulating the scrambled data by means of a pit position modulation (PPM), while the second stage modulation is performed to produce 16-bit output main data from the 16-bit main data by modulating the 16-bit main data by means of a pulse width modulation (PWM).
FIG. 20 illustrates a configuration of the 8/16 modulator 102. As shown in FIG. 20, the 8-bit main data scrambled by the scrambler 101 is not only supplied to a main table 122 and a sub-table 123 via a flip-flop 121 but also directly supplied to a digital sum value (DSV) controller 124. The main data and data representing the next state as selected by a selector 125 are input to the main table 122. Similarly, the main data and the data representing the next state as selected by the selector 125 are input to the sub-table 123.
The main table 122 includes the main data shown in the following Table 1. An 8-bit main data value is searched for by state in the main table 122 and a 16-bit main data word corresponding to the next state is selected and output with reference to the main data shown in Table 1. Similarly, the sub-table 123 includes the sub-data shown in the following Table 2. An 8-bit main data value is searched for by state in the sub-table 123 and a 16-bit main data word corresponding to the next state is selected and output with reference to the sub-data shown in Table 2.
Since the range of the 8-bit main data values is from 0 to 255, 256 sets of 16-bit main data words are defined beforehand in the main table 122 for the respective 8-bit main data values (0 to 255). However, it should be noted that only a part (0 to 45) of the 8-bit main data values (0 to 255) and only a part of the 16-bit main data words corresponding to these 46 values are shown in Table 1. On the other hand, in the sub-table 123, 88 sets of 16-bit main data words are defined for a part (0 to 87) of the 8-bit main data values (0 to 255), unlike the main table 122. However, a smaller part (0 to 45) of the 88 8-bit main data values (0 to 87) and a smaller part of the 16-bit main data words corresponding to the 46 values are shown in Table 2. Furthermore, in both the tables 122 and 123, the next state is defined for each of the 16-bit main data words. Thus, when the 16-bit main data word is searched for, the next state corresponding to the 16-bit main data word is also read out.
TABLE 1 __________________________________________________________________________ Conversion table for 8/16 modulated codes(main) Main State 1 State 2 State 3 State 4 data Code Word Next Code Word Next Code Word Next Code Word Next value MSB LSB State MSB LSB State MSB LSB State MSB LSB State __________________________________________________________________________ 0 0010000000001001 1 0100000100100000 2 0010000000001001 1 0100000100100000 2 1 0010000000010010 1 0010000000010010 1 1000000100100000 3 1000000100100000 3 2 0010000100100000 2 0010000100100000 2 1000000000010010 1 1000000000010010 1 3 0010000001001000 2 0100010010000000 4 0010000001001000 2 0100010010000000 4 4 0010000010010000 2 0010000010010000 2 1000000100100000 2 1000000100100000 2 5 0010000000100100 2 0010000000100100 2 1001001000000000 4 1001001000000000 4 6 0010000000100100 3 0010000000100100 3 1000100100000000 4 1000100100000000 4 7 0010000001001000 3 0100000000010010 1 0010000001001000 3 0100000000010010 1 8 0010000010010000 3 0010000010010000 3 1000010010000000 4 1000010010000000 4 9 0010000100100000 3 0010000100100000 3 1001001000000001 1 1001001000000001 1 10 0010010010000000 4 0010010010000000 4 1000100100000001 1 1001001000000001 1 11 0010001001000000 4 0010001001000000 4 1000000010010000 3 1000000010010000 3 12 0010010010000001 1 0010010010000001 1 1000000010010000 2 1000000010010000 2 13 0010001001000001 1 0010001001000001 1 1000010010000001 1 1000010010000001 1 14 0010000001001001 1 0100000000100100 3 0010000001001001 1 0100000000100100 3 15 0010000100100001 1 0010001001000001 1 1000001001000001 1 1000010001000001 1 16 0010000010010001 1 0010000100100001 1 1000000100100001 1 1000000100100001 1 17 0010000000100010 1 0010000000100010 1 1000001001000000 4 1000001001000000 4 18 0001000000001001 1 0100000010010000 2 0001000000001001 1 0100000010010000 2 19 0010000000010001 1 0010000000010001 1 1001000100000000 4 1001000100000000 4 20 0001000000010010 1 0001000000010010 1 1000100010000000 4 1000100010000000 4 21 0000100000000010 1 0000100000000010 1 1000000010010001 1 1000000010010001 1 22 0000010000000001 1 0000010000000001 1 1000000001001001 1 1000000001001001 1 23 0010001000100000 2 0010001000100000 2 1000000001001000 2 1000000001001000 2 24 0010000100010000 2 0010000100010000 2 1000000001001000 3 1000000001001000 3 25 0010000010001000 2 0100000000100100 2 0010000010001000 2 0100000000100100 2 26 0010000001000100 2 0010000001000100 2 1000000000100010 1 1000000000100010 1 27 0001000100100000 2 0001000100100000 2 1000000000010001 1 1000000000010001 1 28 0010000000001000 2 0100000010010000 3 0010000000001000 2 0100000010010000 3 29 0001000010010000 2 0001000010010000 2 1001001000000010 1 1001001000000010 1 30 0001000001001000 2 0100000100100000 3 0001000001001000 2 0100000100100000 3 31 0001000000100100 2 0001000000100100 2 1001000100000001 1 1001000100000001 1 32 0001000000000100 2 0001000000000100 2 1000100100000010 1 1000100100000010 1 33 0001000000000100 3 0001000000000100 3 1000100010000001 1 1000100010000001 1 34 0001000000100100 3 0001000000100100 3 1000000000100100 2 1000000000100100 2 35 0001000001001000 3 0100001001000000 4 0001000001001000 3 0100001001000000 4 36 0001000010010000 3 0001000010010000 3 1000000000100100 3 1000000000100100 3 37 0001000100100000 3 0001000100100000 3 1000010001000000 4 1000010001000000 4 38 0010000000001000 3 0100100100000001 1 0010000000001000 3 0100100100000001 1 39 0010000001000100 3 0010000001000100 3 1001000010000000 4 1001000010000000 4 40 0010000010001000 3 0100010010000001 1 0010000010001000 3 0100010010000001 1 41 0010000100010000 3 0010000100010000 3 1000010010000010 1 1000010010000010 1 42 0010001000100000 3 0010001000100000 3 1000001000100000 2 1000001000100000 2 43 0010010001000000 4 0010010001000000 4 1000010001000001 1 1000010001000001 1 44 0001001001000000 4 0001001001000000 4 1000001000100000 3 1000001000100000 3 45 0000001000000001 1 0100010001000000 4 1000001001000010 1 0100010001000000 4 __________________________________________________________________________
TABLE 2 __________________________________________________________________________ Conversion table for 8/16 modulated codes(sub) Main State 1 State 2 State 3 State 4 data Code Word Next Code Word Next Code Word Next Code Word Next value MSB LSB State MSB LSB State MSB LSB State MSB LSB State __________________________________________________________________________ 0 0000010010000000 4 0000010010000000 4 0100100001001000 2 0100100001001000 2 1 0000100100000000 4 0000100100000000 4 0100100001001000 3 0100100001001000 3 2 0001001000000000 4 0001001000000000 4 0100100000001001 1 0100100000001001 1 3 0000001001000000 4 0100010000000001 1 1000001000000000 4 0100010000000001 1 4 0000000100100000 3 0100100000000010 1 1001000000000100 3 0100100000000010 1 5 0000000010010000 3 0100001000000000 4 1001000000100100 3 0100001000000000 4 6 0000000001001000 3 0100100000000100 2 1001000001001000 3 0100100000000100 2 7 0000000001001000 2 0100000100000000 4 1001000000000100 2 0100000100000000 4 8 0000000010010000 2 0100100010010000 3 1001000000100100 2 0100100010010000 3 9 0000000100100000 2 0000100000100100 2 1001000001001000 2 0100100000100100 2 10 000001000100000 4 0000010001000000 4 1001001001000000 4 1001001001000000 4 11 0000100010000000 4 0000100010000000 4 1000100001001000 3 1000100001001000 3 12 0001000100000000 4 0001000100000000 4 0100010001001000 3 0100010001001000 3 13 0010001000000000 4 0010001000000000 4 1000100000000100 3 1000100000000100 3 14 0000001000100000 3 0100100000000100 3 1001000010010000 3 0100100000000100 3 15 0000000100010000 3 0100100010010000 2 1001000100100000 3 0100100010010000 2 16 0000000010001000 3 0100001000000001 1 0100100000001000 3 0100001000001001 1 17 0000000001000100 3 0100010000000010 1 0100100010001000 3 0100010000000010 1 18 0000000001000100 2 0100100000100100 3 1001000010010000 2 0100100000100100 3 19 0010000010001000 2 0100100100100000 3 1001000100100000 2 0100100100010000 3 20 0000000100010000 2 0100100100100000 2 0100010001001000 2 0100100100100000 2 21 0000001000100000 2 0100100000010010 1 0100100000001000 2 0100100000010010 1 22 0000010010000001 1 0000010010000001 1 1000100000100100 3 1000100000100100 3 23 0000100100000001 1 0000100100000001 1 1000100010010000 3 1000100010010000 3 24 0001001000000001 1 0001001000000001 1 0100100010001000 2 0100100010001000 2 25 0010010000000001 1 0010010000000001 1 1000100000000100 2 1000100000000100 2 26 0010000001001001 1 0100010000000100 3 1000010000000001 1 0100100000000100 3 27 0000000010010001 1 0100000100000001 1 1000100000000010 1 0100000100000001 1 28 0000000100100001 1 0100010000000100 2 1001000000001001 1 0100010000000100 2 29 0000001001000001 1 0100001000000010 1 1001000000010010 1 0100001000000010 1 30 0001000001000000 4 0000100001000000 4 1000100000100100 2 1000100000100100 2 31 0001000010000000 4 0001000010000000 4 1000100001001000 2 1000100001001000 2 32 0001000100000000 4 0010000100000000 4 0100010000001001 1 0100100000001001 1 33 0000010000100000 3 0000010000100000 3 0100100001001001 1 0100100001001001 1 34 0000001000010000 3 0100010000010010 1 1000100100100000 3 0100010000010010 1 35 0000000100001000 3 0100100000010001 1 1001000000001000 3 0100100000010001 1 36 0000000010000100 3 0100000100000000 4 1001000001000100 3 0100000010000000 4 37 0000010000100000 2 0000010000100000 2 1000001000000001 1 1000001000000001 1 38 0000000010000100 2 0100010000100100 3 1000100010010000 2 0100010000100100 3 39 0000000100001000 2 0100010000100100 2 1000100100100000 2 0100010000100100 2 40 0000001000010000 2 0100100000100010 1 1001000000001000 2 0100100000100010 1 41 0000010001000001 1 0000010001000001 1 1000010000000010 1 1000010000000010 1 42 0000010010000010 1 0000010010000010 1 1000000100000000 4 1000000100000000 4 43 0000100010000001 1 0000100010000001 1 1001000001000100 2 1001000001000100 2 44 0000100100000010 1 0000100100000010 1 1001000000001001 1 1000100000001001 1 45 0001000100000001 1 0001000100000001 1 1001000010001000 3 1001000010001000 3 46 0001001000000010 1 0001001000000010 1 1001000100010000 3 1001000100010000 3 __________________________________________________________________________
In the main table 122, if an input 8-bit main data value is included within the range from 0 to 87, any of the four types of states S1 to S4 shown in Table 1 is selected in accordance with the next state specified by the selector 125. A 16-bit main data word corresponding to the input 8-bit main data value is selected from the 16-bit main data words belonging to the selected state. Then, the selected 16-bit main data word DM is output to a cross-bar switch 126.
On the other hand, if an input 8-bit main data value is included within the range from 88 to 255 in the main table 122 and any of the two types of states S1 and S4 shown in Table 1 is selected in accordance with the next state specified by the selector 125, a 16-bit main data word corresponding to the input 8-bit main data value is selected from the 16-bit main data words belonging to the selected state S1 or S4. Then, the selected 16-bit main data word D1 or D4 is output to the cross-bar switch 126. Furthermore, if an input 8-bit main data value is included within the range from 88 to 255 in the main table 122 and any of the two types of states S2 and S3 shown in Table 1 is selected in accordance with the next state specified by the selector 125, a 16-bit main data word corresponding to the input 8-bit main data value is selected from the 16-bit main data words belonging to the selected state S2 or S3. Then, the selected 16-bit main data word is output to the cross-bar switch 126.
Similarly, if an input 8-bit main data value is included within the range from 0 to 87 in the sub-table 123, any of the four types of states S1 to S4 shown in Table 2 is selected in accordance with the next state specified by the selector 125. And a 16-bit main data word corresponding to the input 8-bit main data value is selected from the 16-bit main data words belonging to the selected state. Then, the selected 16-bit main data word DS is output to the cross-bar switch 126.
At this time, not only the selected 16-bit data words but also the next states corresponding to these 16-bit data words are read out from the tables 122 and 123 and then output to the cross-bar switch 126.
It is noted that the next state is initialized to be 1 in response to a sync code at the beginning of a frame.
When an 8-bit main data value and the next state specified by the selector 125 are input to the DSV controller 124, the DSV controller 124 makes a decision based on the 8-bit main data value and the next state and then outputs a cross-bar switch select signal corresponding to the decision result to the cross-bar switch 126.
In response to the cross-bar switch select signal, the cross-bar switch 126 selects one or two main data word(s) from the 16-bit main data word provided from the main table 122 and the 16-bit main data word provided from the sub-table 123 and then outputs the one or two 16-bit main data word(s) to at least one of a first DSV arithmetic circuit 127 and a second DSV arithmetic circuit 128.
For example, if the DSV controller 124 has determined that the 8-bit main data value is equal to or smaller than 87 and the 16-bit main data word corresponding to the 8-bit main data value exists in each of the main table 122 and the sub-table 123, then the cross-bar switch 126 selects the 16-bit main data words DM and DS from the main table 122 and the sub-table 123, respectively, in response to the cross-bar switch select signal. Then, the cross-bar switch 126 outputs the 16-bit main data words DM and DS to the first and the second DSV arithmetic circuits 127 and 128.
On the other hand, if the DSV controller 124 has determined that the 8-bit main data value is equal to or larger than 88, the 16-bit main data word corresponding to the 8-bit main data value exists only in the main table 122, and either the state S1 or the state S4 has been selected by the next state specified by the selector 125, then the cross-bar switch 126 selects the 16-bit main data word D1 or D4 supplied from the main table 122 in response to the cross-bar switch select signal. Then, the cross-bar switch 126 outputs the 16-bit main data word D1 or D4 to the first and the second DSV arithmetic circuits 127 and 128.
Furthermore, if the DSV controller 124 has determined that the 8-bit main data value is equal to or larger than 88, the 16-bit main data word corresponding to the 8-bit main data value exists only in the main table 122, and either the state S2 or the state S3 has been selected by the next state specified by the selector 125, then the cross-bar switch 126 selects only a single 16-bit main data word (or the 16-bit main data word which has been read out in accordance with either the state S2 or the state S3 specified by the next state) supplied from the main table 122 in response to the cross-bar switch select signal. Then, the cross-bar switch 126 outputs the 16-bit main data word D2 or D3 to the first DSV arithmetic circuit 127.
The selections made by the cross-bar switch 126 from the 16-bit main data words DM, D1, D4 and DS are classified as shown in the following Table 3.
TABLE 3 ______________________________________ Main Data 0 to 87 88 to 255 88 to 255 Value Next S1, S2, S3, S1 or S4 S2 or S3 State S4 Data Select DM from Select D1 or Always Selection main table and D4 correspond- select DM DS from ing to S1 or specified by sub-table S4 from main next state table S2 or S3 from main table ______________________________________
However, in the case where the 8-bit main data value is equal to or larger than 88 and either the state S1 or the state S4 has been selected in accordance with the next state specified by the selector 125, if the run length of successive codes having an equal sign between an 8-bit main data word and a previous 8-bit main data word is out of the range from 2 to 10 in either the state S1 or the state S4, then the DSV controller 124 controls the cross-bar switch 126 such that only a 16-bit main data word D1 or D4 belonging to the state S1 or S4 and having a run length within the range from 2 to 10 is selectively output. Thus, in order to output the 16-bit main data words D1 and D4 from the main table 122 to the first and the second DSV arithmetic circuits 127 and 128, the run length of the successive codes having an equal sign between an 8-bit main data word and a previous 8-bit main data word is required to be within the range of 2 to 10.
Every time a 16-bit main data word is input to the first arithmetic circuit 127 and/or the second arithmetic circuit 128, the arithmetic circuit(s) calculate(s) a digital sum value (DSV) associated with the input 16-bit main data word. The algorithm used for calculating the DSV is as follows.
For example, if a 16-bit main data word such as that shown in FIG. 21A is input from the cross-bar switch 126 to a PWM modulator 129 via the selector 125, the PWM modulator 129 performs a pulse width modulation on the 16-bit main data word, thereby producing and outputting a 16-bit output main data word such as that shown in FIG. 21B.
As can be seen from the comparison between FIGS. 21A and 21B, the number of "1" bits and the number of "0" bits included in a single output main data word can be derived from a single 16-bit input main data word. Thus, every time a single 16-bit main data word is input, the number of "1" bits and the number of "0" bits included in a single output main data word corresponding to the single 16-bit input main data word are obtained and then the difference between the numbers is calculated. The differences calculated for the respective words are accumulated, thereby obtaining a DSV. The DSVs calculated by the first and the second DSV arithmetic circuits 127 and 128 are supplied to the selector 125 and a comparator 130. In actuality, the "1" bit included in a single output main data word is replaced by a value "+1" and the "0" bit included in the single output main data word is replaced by a value "-1". The total sum of the values "+1" and "-1" is calculated in each output main data word. Then, the sums are accumulated for the respective words, thereby obtaining the DSV.
In addition, the calculation is performed by the first and the second DSV arithmetic circuits 127 and 128 on a sector basis, and is continuously performed from the beginning to the end of a single sector. At the beginning of a sector, the first bit (or the least significant bit LSB) of the sector is input from the PWM modulator 129 to the first and the second DSV arithmetic circuits 127 and 128 and the first value of the output main data word is initialized or set to be equal to zero in response to the bit LSB.
When the DSVs are input from the first and the second DSV arithmetic circuits 127 and 128 to the comparator 130, the comparator 130 selects either one of the DSVs having a smaller absolute value and then provides the information indicating the arithmetic circuit 127 or 128 which has calculated the selected DSV for the selector 125. In response to the information, the selector 125 selects the arithmetic circuit 127 or 128 indicated by the comparator 130, outputs the 16-bit output main data word from which the DSV has been calculated by the arithmetic circuit 127 or 128 to the PWM modulator 129, and outputs the next state associated with the 16-bit output main data word to the main table 122, the sub-table 123 and the DSV controller 124.
That is to say, in the 8/16 modulator 102, 8-bit input main data words are modulated into corresponding 16-bit main data words, the DSV of the respective output main data words corresponding to the 16-bit main data words is calculated beforehand, the 16-bit main data words, from which a smaller DSV can be derived, are selected and then the 16-bit main data words are modulated into the 16-bit output main data words so as to be output. However, as mentioned above, if the 16-bit main data word corresponding to the input 8-bit main data value exists only in the main table 122 and either the state S2 or the state S3 has been selected by the next state specified by the selector 125, then only a single 16-bit main data word (or the 16-bit main data word which has been read out in accordance with either the state S2 or the state S3 specified by the next state) is selected from the main table 122. Thus, the modulation from the 16-bit main data word to the 16-bit output main data word is performed.
A series of processing steps performed by such a code conversion apparatus will be described with reference to the flow charts shown in FIGS. 22 and 23.
First, after the top of a frame has been identified by counting the respective bits of an input main data word (Step 201), a sync code is added to the top of the frame (Step 202) and the next state output from the selector 125 of the 8/16 modulator 102 is initialized to be S1 (Step 203). Then, if it is determined that the end of a sector has not been reached (Step 204, NO), then the processing returns to Step 201.
Subsequently, the scrambling of the frame of the input main data word is started (Step 205) and the frame of the scrambled main data word is converted into the frame of an output main data word on a word basis (Step 206). Then, if the top of the next frame is identified (Step 201), a sync code is added to the top of the frame (Step 202) and the next state is initialized again to be S1 (Step 203). Next, the scrambling and the conversion are performed (Steps 205 and 206). From then on, similar processing is repeatedly performed on the respective frames. And when the end of a sector has been reached (Step 204, YES), the processing of one sector ends.
Moreover, after Step 206 has been performed, it is also determined whether or not the 8-bit main data value is smaller than 88. As shown in FIG. 23, if the value is smaller than 88 (Step 301, YES), then a 16-bit main data word having a smaller DSV is selected from the 16-bit main data word DM supplied from the main table 122 and the 16-bit main data word DS supplied from the sub-table 123 (Step 302).
On the other hand, if the 8-bit main data value is equal to or larger than 88 (Step 301, NO), then a 16-bit main data word D1 or D4 having a smaller DSV is selected from the main table 122 (Step 303).
If an output main data word always having a smaller DSV is produced in this manner, then the low frequency components of the main data word are reduced. Thus, in a recording/reproducing apparatus for recording and/or reproducing the main data word onto/from a recording medium, the low frequency components of a reproduced signal can be reduced, the shift of the envelope of the reproduced signal can be suppressed, and a reproduction error can be prevented to a certain degree.
However, though the above-described prior art code conversion apparatus can surely reduce the low frequency components of a reproduced signal and the possibility of the abnormal increase of the low frequency components, the degree of the reduction is not satisfactorily high and a reproduction error may continue to occur in some cases.
More specifically, when there are M types of 16-bit main data words in the 8/16 modulator 102 shown in FIG. 20, N types of 16-bit main data words having bit patterns causing the DSV to diverge are included in the M types of 16-bit main data words. Thus, if 16-bit main data words having such bit patterns successively appear, then the DSV adversely increases or decreases to diverge. As a result, the low frequency components of the output main data words are disadvantageously increased.
In the above-described conventional example, M=256 and N=168. When the 8-bit main data value is within the range from 0 to 87, the DSV converges. On the other hand, when the 8-bit main data value is in the range from 88 to 255, the DSV diverges. In actuality, the divergence of the DSV occurs in about 10% of the entire main data. FIG. 24A is a graph showing the variation of the 8-bit main data values in one sector and FIG. 24B is a graph showing the increase and the decrease of the DSV in accordance with the variation of the 8-bit main data values. As can be seen from these graphs, if the 8-bit main data values are continuously included within the range from 88 to 255, the DSV diverges.
That is to say, in the prior art code conversion apparatus, though the input main data is scrambled and the scrambled main data is subjected to an 8/16 modulation, the low frequency components of the main data cannot be satisfactorily reduced. Consequently, when the main data is reproduced from a recording medium on which the main data has been recorded, the low frequency components of the reproduced signal increase, the envelope of the reproduced signal abruptly varies, and a reproduction error occurs. Even if the envelope of the reproduced signal is corrected or the main data is corrected by using an error correction code (ECC) to be added thereto, such a reproduction error cannot be totally prevented.
In addition, since a set of pseudo-random number sequences are sequentially rearranged in a predetermined order, it is possible that substantially the same signal is repeatedly rewritten on the same sector. In such a case, since the characteristics of a part of the recording medium occupied by the sector in question become nonuniform, the S/N ratio of the reproduced signal is decreased and a reproduction error occurs in some cases.